This invention relates in general to the field of electronics and more particularly to a programmable burst FIFO buffer.
Typical first-in-first-out (FIFO) devices such as FIFO buffers allow only one word to be stored at a time, with the device or system that the FIFO is being used with having to check that the, FIFO is not full after each subsequent word is loaded. This limitation presents problems for systems using interfaces such as RAMBUS that need to have multiple words or bursts of data loaded at any given point in time.
Current FIFO designs have to be conservative as to when to trigger the full or empty flags because the flags may glitch. In order to be conservative some current FIFO buffer designs report full or empty buffers when it is not necessarily the case in order to protect against overflows or underflows when writing to the buffer. Glitches can occur due to the write and read sides being in different clock domains. A need thus exists for a FIFO device that can alleviate some of the problems mentioned above.